Implementation and study of quaternary multiplexer using universal set of gates

Multi-value logic is defined as a non-binary logic and involves the switching between more than two states. The design of Multiple Valued Logic (MVL) digital circuits is performed by increasing the representation domain from the two level (N=2) switching algebra to N > 2 levels. More data can be transmitted by single wire having more than two levels. Multiple-valued logic (MVL) application in the design of digital devices opens large number of opportunities. It can reduce number of active elements and number of interconnection lines. In this paper we have studied universal set of quaternary gates which are further used for designing quaternary multiplexer. The circuit is designed in VHDL using ModelSim simulator. Structural modelling technique is used for designing the quaternary multiplexer.